Olivia Weng, Marta Andronic, Danial Zuberi, Jiaqing Chen, Caleb Geniesse, George A. Constantinides, Nhan Tran, Nicholas Fraser, Javier Mauricio Duarte, Ryan Kastner. Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT. In submission.
Colin Drewes, Tyler Sheaves, Olivia Weng, Keegan Ryan, William Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond. Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters. In ACM Transactions on Reconfigurable Technology and Systems (TRETS) 17, 3, Article 49. September 2024.
Olivia Weng, Andres Meza, Quinlan Bock, Benjamin Hawks, Javier Campos, Nhan Tran, Javier Duarte, Ryan Kastner. FKeras: A Sensitivity Analysis Tool for Edge Neural Networks. In ACM Journal on Autonomous Transportation Systems 1, 3, Article 15. September 2024.
Colin Drewes, Olivia Weng, Andres Meza, Alric Althoff, Bill Hunter, David Kohlbrenner, Ryan Kastner, Dustin Richmond. Pentimento: Data Residue in Cloud FPGAs. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). San Diego, CA. April 2024.
Tommaso Baldi, Javi Campos, Ben Hawks, Jennifer Ngadiuba, Nhan Tran, Daniel Diaz, Javier Duarte, Ryan Kastner, Andres Meza, Melissa Quinnan, Olivia Weng, Caleb Geniesse, Amir Gholami, Michael W. Mahoney, Vladimir Loncar, Philip Harris, Joshua Agar, Shuyu Qin. Reliable edge machine learning hardware for scientific applications. In IEEE 42nd VLSI Test Symposium (VTS). Tempe, AZ. April 2024.
Olivia Weng, Gabriel Marcano, Vladimir Loncar, Alireza Khodamoradi, Abarajithan G, Nojan Sheybani, Andres Meza, Farinaz Koushanfar, Kristof Denolf, Javier Mauricio Duarte, Ryan Kastner. Tailor: Altering Skip Connections for Resource-Efficient Inference. In ACM Transactions on Reconfigurable Technology and Systems (TRETS) 17, 1, Article 11. January 2024.
Olivia Weng, Gabriel Marcano, Vladimir Loncar, Alireza Khodamoradi, Nojan Sheybani, Kristof Denolf, Farinaz Koushanfar, Javier Duarte, Ryan Kastner. Adapting Skip Connections for Resource-Efficient FPGA Inference. In Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA). Monterey, CA. February 2023.
Colin Drewes, Olivia Weng, Keegan Ryan, William Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond. Turn on, Tune in, Listen up: Maximizing Channel Capacity in Time-to-Digital Converters. In Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA). Monterey, CA. February 2023. Nominated for Best Paper.
Hendrik Borras, Giuseppe Di Guglielmo, Javier Duarte, Nicolò Ghielmetti, Ben Hawks, Scott Hauck, Shih-Chieh Hsu, Ryan Kastner, Jason Liang, Andres Meza, Jules Muhizi, Tai Nguyen, Rushil Roy, Nhan Tran, Yaman Umuroglu, Olivia Weng, Aidan Yokuda, Michaela Blott. Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark. In Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware (MLBench) at Conference on Machine Learning and Systems (MLSys). August 2022.
Olivia Weng. Neural Network Quantization for Efficient Inference: A Survey. arXiv:2112.06126. December 2021.
Colin Drewes, Steven Harris, Winnie Wang, Richard Appen, Olivia Weng, Ryan Kastner, William Hunter, Christopher McCarty, Dustin Richmond. A Tunable Dual-Edge Time-to-Digital Converter. In IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). Virtual, May 2021.
Michael Barrow, Olivia Weng, and Ryan Kastner. Design Space Exploration for Machine Learning Architectures. In Workshop on Reimagining Codesign hosted by US DOE, Office of Advanced Scientific Computing Research. Virtual, March 2021.
Olivia Weng, Alireza Khodamoradi, and Ryan Kastner. Hardware-efficient Residual Networks for FPGAs. In Proceedings of Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA) at Design, Automation and Test in Europe (DATE). Grenoble, France (Virtual), February 2021.
Olivia Weng and Andrew A. Chien. Evaluating Achievable Latency and Cost: SSD Latency Predictors. In Workshop on Accelerated Machine Learning (AccML) at High Performance Embedded Architectures and Compilers (HiPEAC). Bologna, Italy, January 2020.