Olivia Weng

computer architect.

oweng at ucsd edu

Curriculum vitae


  1. Olivia Weng, Gabriel Marcano, Alireza Khodamoradi, Nojan Sheybani, Farinaz Koushanfar, Kristof Denolf, Javier Duarte, Ryan Kastner. Tailor: Altering Skip Connections for Resource-Efficient Inference. In submission.

  2. Colin Drewes, Olivia Weng, Keegan Ryan, William Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond. Turn on, Tune in, Listen up: Maximizing Channel Capacity in Time-to-Digital Converters. In submission.

  3. Michaela Blott, Hendrik Borras, Giuseppe Di Guglielmo, Javier Duarte, Nicolò Ghielmetti, Ben Hawks, Scott Hauck, Shih-Chieh Hsu, Ryan Kastner, Jason Liang, Andres Meza, Jules Muhizi, Tai Nguyen, Rushil Roy, Nhan Tran, Yaman Umuroglu, Olivia Weng and Aidan Yokuda. Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark. In Workshop on Benchmarking Machine Learning Workloads on Emerging Hardware (MLBench) at Conference on Machine Learning and Systems (MLSys). To appear.

  4. Olivia Weng. Neural Network Quantization for Efficient Inference: A Survey. arXiv:2112.06126. December 2021.

  5. Colin Drewes, Steven Harris, Winnie Wang, Richard Appen, Olivia Weng, Ryan Kastner, William Hunter, Christopher McCarty, Dustin Richmond. A Tunable Dual-Edge Time-to-Digital Converter. In IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). Virtual, May 2021.

  6. Michael Barrow, Olivia Weng, and Ryan Kastner. Design Space Exploration for Machine Learning Architectures. In Workshop on Reimagining Codesign hosted by US DOE, Office of Advanced Scientific Computing Research. Virtual, March 2021.

  7. Olivia Weng, Alireza Khodamoradi, and Ryan Kastner. Hardware-efficient Residual Networks for FPGAs. In Proceedings of Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA) at Design, Automation and Test in Europe (DATE). Grenoble, France (Virtual), February 2021.

  8. Olivia Weng and Andrew A. Chien. Evaluating Achievable Latency and Cost: SSD Latency Predictors. In Workshop on Accelerated Machine Learning (AccML) at High Performance Embedded Architectures and Compilers (HiPEAC). Bologna, Italy, January 2020.


On taking walks after lunch
Nov 29, 2019
In which I reflect on the joys of taking walks
3 minute read