Welcome to CMPE 120! We’re so happy to have you in this course. Many of you have been writing programs for a couple of years now, and they have always run on computer hardware. The cool part was that you were able to learn how to program without needing to think much about how the hardware executed your code. But, at some point in your software engineering career, you will be confronted with the fact that some hardware is running your code—and something is going wrong with the way they are interacting. Not only does it impact your program, but also that of your colleagues! Oh no! This course will help demystify why this is happening and how to fix it, turning you into an even stronger software engineer.
Please read the official course syllabus with all the grading information.
The current schedule is tentative and subject to change depending on how the class progresses. Slides and assignments will be posted in the schedule below. The classes listed as (async) will not be held in-person. They will instead be posted as recorded lectures on Canvas.
For the suggested reading, we will be using these textbooks:
| Week | Date | Lecture Topic | Homework | Suggested Reading |
|---|---|---|---|---|
| 0 | Thu, Aug 20 | Introduction | HW0 out | |
| 1 | Tue, Aug 25 | Intro to C & binary representation | DIS 1.1 - 1.4 | |
| Thu, Aug 27 | More binary representation & overflow | HW0 due | DIS 4.1 - 4.5 | |
| 2 | Tue, Sep 1 | Binary wrap-up & strings | DIS 1.5 | |
| Thu, Sep 3 | Unicode & bitwise operators | HW1 out | DIS 4.6 | |
| 3 | Tue, Sep 8 | Intro to memory and pointers (async) | DIS 2.1 - 2.3 | |
| Thu, Sep 10 | Pointers & arrays, dynamic memory allocation (async) | DIS 2.4 - 2.5 | ||
| 4 | Tue, Sep 15 | Structs, dynamic data structures (linked lists) | DIS 1.6, DIS 2.7 | |
| Thu, Sep 17 | Intro to ISA & assembly | HW1 due; HW2 out | P&H 1.1 - 1.3, P & H 2.1 - 2.3 | |
| 5 | Tue, Sep 22 | Conditional control & gdb; HW1 quiz | P&H 2.7, DIS 3.1 - 3.2 | |
| Thu, Sep 24 | More gdb & procedures | P&H 2.8 | ||
| 6 | Tue, Sep 29 | The performance equation and Amdahl’s Law | P&H 1.6 - 1.7 P&H 1.10 | |
| Thu, Oct 1 | The single cycle processor | HW2 due; HW3 out | P&H 4.1, 4.3 - 4.4 | |
| 7 | Tue, Oct 6 | Pipelining & instruction level parallelism; HW2 quiz | P&H 4.5 - 4.6 | |
| Thu, Oct 8 | Pipelining & instruction level parallelism | P&H 4.7 | ||
| 8 | Tue, Oct 13 | MIDTERM EXAM | ||
| Thu, Oct 15 | Speculation | HW3 due; HW4 out | P&H 4.8 | |
| 9 | Tue, Oct 20 | Speculation; HW3 quiz | P&H 4.10 | |
| Thu, Oct 22 | Memory hierarchy & caches | P&H 5.1 - 5.3 | ||
| 10 | Tue, Oct 27 | Caches locality and design | P&H 5.4 | |
| Thu, Oct 29 | Caches and your programs | P&H 5.4 | ||
| 11 | Tue, Nov 3 | Virtual memory & paging | P&H 5.7 | |
| Thu, Nov 5 | Virtual memory & paging | HW4 due; HW5 out | P&H 5.7 | |
| 12 | Tue, Nov 10 | Memory level parallelism (loop unrolling); HW4 quiz | None | |
| Thu, Nov 12 | Memory level parallelism (data structure analysis) | None | ||
| 13 | Tue, Nov 17 | Superscalar & VLIW architectures | None | |
| Thu, Nov 19 | Multicore, SMT | HW5 due | P&H 6.2, 6.4 | |
| 14 | Tue, Nov 24 | Security (cache side-channel attacks) | None | |
| Thu, Nov 26 | NO CLASS - Happy Thanksgiving! | |||
| 15 | Tue, Dec 1 | SIMD & GPU architectures; HW5 quiz | P&H 6.3, 6.6 | |
| Thu, Dec 3 | Systolic arrays & hardware-software codesign | None | ||
| 16 | Thu, Dec 10 | FINAL EXAM - SEC 01 | ||
| 17 | Tue, Dec 15 | FINAL EXAM - SEC 02 |
Many parts of this course are thanks to Leo Porter and Pat Pannuto.